Semiconductor fabrication typically requires fabricating multiple layers on a structure in which some or all of the layers include patterned features. Overlay metrology is the measurement of the relative positions of structures on various layers of a sample, which are critical to the performance of a fabricated device and must typically be controlled within tight tolerances. For example, overlay metrology may measure the relative positions of features on different sample layers as a measure of the layer-by-layer alignment of fabrication tools.
Overlay measurements are commonly performed on dedicated overlay targets having features designed for sensitive overlay measurements rather than directly on device features. Features on different layers of overlay targets are commonly spatially separated to avoid overlap and facilitate measurements of features on buried layers. For example, an overlay target element on one layer may impact a measurement of an overlay target element on a previously-fabricated layer. However, open areas associated with spatially separated target elements may not be compatible with microelectronics fabrication. Further, device features commonly include stacked structures such that overlay measurements of spatially separated overlay target elements may introduce measurement errors.
It is therefore desirable to provide systems and methods for measuring overlay on stacked overlay target elements.